EISC
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EISC (Extendable Instruction Set Computer) is a compressed code processor architecture developed for embedded applications. The architecture is developed by Advanced digital chips inc, Seoul, Korea.(http://www.adc.co.kr)
While achieving high code density and a low memory access rate, the EISC architecture adopts a novel and terse scheme to resolve the problem of insufficient immediate operand fields of the compressed code architectures.
The EISC uses an efficient fixed length 16-bit instruction set for 32-bit data processing. To resolve the problem of insufficient immediate operand fields in a concise way, EISC uses an independent in struction called load extension register(LERI), which consists of a 2-bit opcode and a 14-bit immediate value.
The LERI instruction extends the immediate field by loading an immediate value to a special register called the extension register. By using LERI instructions, the EISC architecture can make the program code more compact than the competing architectures, since the frequency of LERI instructions is less than 20% in many programs. In addition, EISC does not require instructions for switching its processor mode between the compressed instruction mode and the normal instruction mode. (For competing architectures, extra mode-changing instructions are added to use specific instructions such as MAC instructions.)
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[edit] Processor Family
EISC has 16-bit, 32-bit and 64-bit embedded microprocessor family. There exist SE(simple EISC) series and AE(Advanced EISC) series.
[edit] See also
[edit] External links
[edit] General Links
[edit] Related Papers
- High-performance extendable instruction set computing
- AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core in ETRI Journal, Volume 25, Number 5, October 2003
- A DSP-enhanced 32-bit embedded microprocessor
- An automated, reconfigurable, low-power RFID tag
- Design of a DSP Unit for 32-bit Embedded EISC Microprocessor
- Supports for Processing Media Data in Embedded Processors
