Talk:Field effect transistor

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This article was externally reviewed on December 14, 2005 by Nature. It was found to have 3 errors.

Contents 1 Correction 2 mosfet symbols 3 MOSFET section 4 External links 5 Analog circuits 6 basic circuits 7 BJTs as voltage controlled resistors 8 Errors ID'd by Nature, to correct 9 Behavior of d mode FETs 10 What's the difference between an NPN transistor and a FET? 11 Field Effect Transistors as Light Detectors 12 Pinch off description... wrong or misleading!!

[edit] Correction

Most of what I've done here doesn't need any explanation, but there's one correction I think warrants a note. I replaced every instance of "glass" with "oxide". This is because the silicon dioxide layer under a gate is not glass. Glass would not work. A glass is an amorphous solid - irregular arrangement of atoms. The common usage of "glass" happens to be an instance of this. SiO₂ in MOSFETs is crystalline, not glass. -- Tim Starling

Small correction: amorphous oxides can work perfectly well as gate oxides. see link. At least as far as I know, these films are almost entirely amorphous. The best films are done with ECR, but you can also use PECVD and get decent results. On physical grounds, I don't see any reason why a gate dielectric has to be crystalline in "work". --User:Dgrant

You're the man Dave, I'll take your word for it. Before you came along, I didn't know amorphous oxides were used for anything other than window glass :) I notice that the resistivity of the oxide in your reference is many orders of magnitude less than for crystalline silicon. That would degrade performance somewhat, but at least the breakdown voltage is still high. -- Tim Starling

"Oxide" is more correct than "Glass". A glass is not only amorphous but it also contains lots of impurities of highly mobile ions as softener, making it very inadequate as gate oxide. Dgrat is right about amourphous oxides, although they will result in very instable transistors. In organic transistors, even polymers are used as gate dieletric. --Qdr 17:12, 17 Jul 2004 (UTC)

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what does "whereas those to the left abstract from the body contact." mean? It doesn't make any sense to me, or at least is doesn't convey the indended meaning, in my mind. dave

It doesn't mean anything. I changed it to something which makes sense, and is probably right. I seem to remember seeing some FET-like structures with the body insulated from the backside, but I don't think they do that for MOSFETs. -- Tim Starling 00:39 May 14, 2003 (UTC)

You have that in SOI (Silicon on Insulator) FETs, but these work slightly different.--Qdr 17:12, 17 Jul 2004 (UTC)

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I edited the terminals section. I didn't see any discussion about it on this page. All FET's have 4 terminals (except possibly JFETs, but I'm pretty sure they do. I'll check on this and add an exception if they don't). Most of the time they are connected internally because the body effect is only useful in a couple of cases and is detrimental in most others. There are times that it doesn't matter.

The internal connection is made for three reasons. The first is to simplify circuit design. Why have a 4th terminal come out of the package if it's just going to be connected to one of the others. The second is to reduce the cost of the package. A fourth terminal adds to cost and complexity of the package, especially since there are times that you want the body to be at a very different voltage then the source. The third reason is that there is some resistance to the leads and in some cases, such as high tempreature and high current use, that resistance can cause the small current running along the body lead and the large current running along the source lead to create a measurable differential between the body and source voltages. This causes a measurable amount of difference in the threashold voltage due to the body effect, which will cause irregular switching voltages in digital circuits and plays havoc with the gain in analog circuits. By making the connection internally the designer can help to negate those effects and keep the source and body as close in voltage as possible. High frequency switching can also bring the body effect into play because there is a measurable current flowing from the gate to the body due to the capacitance.

I can think of two, possibly three, times that one would want a seperate body connection. The first is in digital designs, where you can better control the switching characteristics by connecting the body of the N-channel to the GND and the body of the P-channel to Vdd because the source may be connected to another FET's drain. The second is in analog FET switches, where one takes an N-channel and connects its drain and source in parallel with a P-channel (Although in this case they are simple FET's, which don't have a drain or source. The parasitic diode of the FET is actually designed in). The body of the P-channel goes to Vdd and the N-channel to GND. The gate of the N-channel gets driven with a signal to Vdd and the P-channel gets driven with the N-channel signal inverted. As the N-channel gate goes high, the P-channel gate goes low. This design allow the passing of analog signals higher than Vdd and lower than GND. The only limit on amplitude is Vds max. The third I am not sure about because I can't remember if biasing the base seperately gave the FET better temp characteristics or worse. It was either to stabalize it or make it into a device capable of reading tempreatue. I'll look it up and maybe find a place for it on the MOSFET page. --Jeffrobins

[edit] mosfet symbols

The schematic for your MOSFET shows a solid line connecting the Source and Drain. Does this not indicate a depletion mode MOSFET?. An enhancement mode MOSFET is symbolically shown with a dashed line between the Source and Drain.

The arrows for the 'metallurgical' contacts point at the bottom of the N diffusions. The metal contact is on the top surface. Shouldn't your arrows point to the upper surface of the N regions?.

All textbooks use different notations. I can't remember right now what is right, and what is depletion, enhancement, etc... However, should use standard IEEE conventional symbols, whatever those are, and we should state that they are the IEEE standard symbols. If there are some common "misuses" of the symbols out there, then we should mention that. So first thing I think is to check IEEE and see if there are standard symbols, and secondly to check something like Art of Electronics and see what it uses. dave 22:06, 16 Oct 2003 (UTC)

IEEE: http://ewh.ieee.org/soc/es/Nov1998/14/education/

You are right about the 'metallurgical' junctions, they are on top of the diffusion region and are not the same! Modern FETs do not only use high doping, but also metal silicides at this place.--Qdr 17:12, 17 Jul 2004 (UTC)

[edit] MOSFET section

I'm planning on doing a lot of work on the MOSFET section. I hope to discuss how MOSFETs are evolving to smaller and smaller submicron dimensions, and the problems designers are encountering...obviously non-technically. I've created two subcategories I want to expand upon--why MOSFETs are so popular and the problems with scaling. Rmalloy 13:47, 14 Jul 2004 (UTC)

I think some work needs to be done in the introduction to MOSFET...most important part. for later. Rmalloy 18:38, 14 Jul 2004 (UTC)

Thanks for your efforts! I assume at some point it would make sense to put all MOSFET stuff in separate article. Agreement? Pjacobi 19:26, 14 Jul 2004 (UTC)

I dunno, I'm new here and don't know what the protocols are. As long as info is easily accessible it makes little difference to me. I'm not going to touch stuff like that. Rmalloy 20:06, 14 Jul 2004 (UTC)

It could make sense to have a rather generic introduction to FETS on this page and move all the details (different types, processing, materials) to other pages. --Qdr 17:12, 17 Jul 2004 (UTC)

• • • • Splitup plan, please comment under each point if necessary. If no active disagreement is seen, I'll do the splitup around 2004-07-19 21:00 UTC. Pjacobi 18:49, 18 Jul 2004 (UTC)
        • The MOSFET specific parts of Field Effect Transistor will be moved.
        • This applies to section MOSFET (currently 1.1) and DMOS (currently 1.5).
        • It will go to http://en.wikipedia.org/w/wiki.phtml?title=MOSFET&redirect=no which is currently a redirect.
        • The JFET, MESFET, and HEMT sections are not yet substantial enough to be moved to separate articles.

Sounds good, but I think also the other types of FET devices should be moved somewhere as they are way too specialized for a generic introduction. Maybe an article about "special" or "exotic" FETs? --Qdr 19:59, 18 Jul 2004 (UTC)

Lumping together JFETs and MESFETSs into Field effect transistor (exotic) (or [[Field effect transistor (bizarre)]?) will break my heart ;-). I'd vote keeping them (temporarily) in the main article, or as a second choice, make all separate articles, even when HEMT will be a short one. Pjacobi 21:34, 18 Jul 2004 (UTC)

I vote for separate articles, maybe that is also an incentive to extend the individual articles a little. And btw, there should also be a link to TFTs in the main FET article. --Qdr 22:17, 18 Jul 2004 (UTC)

I second this. With some diagrams all of these transistor types would be good separate articles. I think Field effect transistor should be a list of links. Maybe some generic discussion. Rmalloy 00:14, 19 Jul 2004 (UTC)

Rmalloy: There are some inaccuracies in your additions: The reason for using polysilicon as a gate material is the reduction of interface states and the self aligned S/D diffusion. Replacing it with metals (for example TaN, TiN) is subject of current research. Current gate oxide thicknesses are way below the 20nm you stated, I changed it to 2nm. But somebody should look up an accurate number. The problem with thin oxides is not breakdown, but leakage by quantum mechanical tunneling of electrons through the oxide. To remedy this, the industrie works on high-k dielectrics.--Qdr 17:41, 17 Jul 2004 (UTC)

QDR: First-off, I must admit that I haven't worked in this area for 2 years. But I think I am right about the polysilicon gate. The self-aligned S/D diffusion process would work equally well with a metal gate. I went back and looked at some stuff I wrote on www.everything2.com when I was a grad student in this area. Look at the article MOSFET that describes and shows diagrams of the fabrication process. The self-alignment process work the same if the gate were aluminum. I'm 99% sure that the reason you can't use aluminum is that there is a high-temperature annealing step after the gate is deposited, and this would melt aluminum. Now the reason the annealing must be done after the gate is deposited relates to the self-alignment process (S/D to be annealed created after gate), so we could be both right in a sense.

I looked up the melting points of the metals you mention, and they have very high melting points. When I was a grad student, I don't recall much effort into using these metals as gates. I don't know why, so I won't argue. But I do remember heavy emphasis on the silicides, like I wrote in this article. I know what surface states are, but I don't see how they relate.

2nm is the accurate number. I meant 20 angstroms. 2nm was considered an absolute cutoff.

Now my memory is that 2nm is still a long way for an electron to tunnel. I seem to recall that, like I said, the oxide broke down, creating states in the oxide that acted like rocks across a river that you can jump across, facilitating tunneling. So I won't argue with you here...we might both be right. And it's not worth arguing. But I'm 99% sure that 2nm was the cutoff, considered absolute by the chief technology officer of TSMC. And I agree about the high-K dielectrics, and mentioned it in the article. Rmalloy 18:54, 17 Jul 2004 (UTC)

I did some quick websearching. An Intel site claims successful operation with 1.2nm of gate oxide, so I guess I'll have to bite my tongue on 2nm. And I'm reminded of another key issue for gate materials--work function. The current setup, where the source, drain, and gate are all doped heavily at the same time gives the gates the proper work function for the transistor type--NMOS or PMOS. Successful metal gate processes would require two kinds of metals--one work function for each transistor-type. It's dawning on me that the choice of gate materials involves several issues, including all the ones we've mentioned and probably several more.

Feel free to clean up, correct, or add to anything I wrote. These issues are complex and there are many issues to discuss...maybe it would be best to avoid difficult issues like this altogether in an encyclopedia. Phew I'm glad I left this field! Rmalloy 16:35, 18 Jul 2004 (UTC)

The oxide thickness is a moving target, IMO around 2nm is a good guess. Intels 1.2 nm oxide was probably already nitrited oxide. There are many candidates for new metal gates, however the ones I quoted have been announced by the IMEC recently. And yes, there are various leakage mechanisms (poole frenkel, schottky emission into insulator valence band, direct tunneling, fowler-Nordheim) and they are enhanced by soft breakdown, however they are usually not regarded as breakdown itself.

I am pretty sure that the main incentive to use polysilicon gates was the self aligning SD process, back in the 70ies. I do not know the exact problem with Al gates and the self aligning process, but for example the spacer oxide would be pretty difficult to apply to an Al-Gate. Anyways, all of this is way too detailed for a Wikipedia article, the best way is to formulate it as generic as possible. --Qdr 19:59, 18 Jul 2004 (UTC)

Good point about the spacer. I have the melting thing stuck in my head...I must have picked it up somewhere. I agree this is all too detailed for Wikipedia, but I guess I thought some explanation for the polysilicon gate would be advisable. At first glance, polysilicon is a very strange choice for gate material. You obviously know what you're talking about, so don't hesitate to delete or change anything I wrote. Rmalloy 00:14, 19 Jul 2004 (UTC)

[edit] External links

IMHO the external link [1] is somewhat obscure - and I'm a member of that Yahoogroup! It's neither focused on FETs nor well known. I plan to remove the link when I have some better to provide. Pjacobi 19:26, 14 Jul 2004 (UTC)

Yeah, that's a dubious link. Interesting group though.

Please remove it, I think its just a commercial plug - the whole yahoo group is. --Qdr 17:12, 17 Jul 2004 (UTC)

[edit] Analog circuits

I've added all I feel comfortable adding about MOSFETs in analog circuits. I wish someone could discuss analog stuff, since everything is so digital digital digital. Rmalloy 23:38, 14 Jul 2004 (UTC)

Added an explanation of how FETs actually work. Pinchoff and all that. --Wjbeaty 08:17, Apr 3, 2005 (UTC)

Sorry, I see that you had quite a bit of work with your recent addition. However, I don't think it belong to this article and thus reverted it.

*You explained the operation of a JFET only. This is a rarely used special type of FET, the explanation does not apply to common MOSFETS. Maybe you could improve the JFET section?

*The operation of the different types of field-effect transistors is already explained in the articles for the respective devices. There is no need for detailed information about the operation in the main article. See also thread above. --Qdr 11:57, 3 Apr 2005 (UTC)

"You explained the operation of a JFET only" What? Please justify such a statement. As I understand it, you're completely incorrect. Which part of my explanation do you think doesn't apply to all types of FETs? (Ah, I see one issue: the present MOSFET article only describes enhancement-mode devices, not MOSFETs in general. Perhaps I should move this analog/pinchoff explanation to both JFET and MOSFET articles rather than having a general FET explanation here.)

Also, please indicate where on WP the "pinchoff" phenomenon is explained. I don't get any search hits at all. This stuff is common to all FETs: it's the essence of the "analog mode" explanation of FET operation. Could you explain why it doesn't belong in the main article? Should there be a separate article to explain generalized FET operation (including pinchoff mechanism?)

I note that Rmalloy says above, "I wish someone could discuss analog stuff." I attempted to do so. Rather than removing it, shouldn't you post your own version of a general analog-based FET explanation? Or if you object to specific details of my analog explanation, please edit them. --Wjbeaty 02:22, Apr 4, 2005 (UTC)

A quesiton: "The MOSFET's strengths as the workhorse transistor in most digital circuits does not translate into supremacy in analog circuits, in which the bipolar junction transistor (BJT) has traditionally been seen as the transistor of choice, due largely to its high gain." This does not seem correct, since FETs have near-infinite gain - essentially no current flows into the gate. Glengarry 21:09, 15 Jul 2004 (UTC)

Bad subject-verb agreement for one thing :(.

Ok, this is not an area I know a lot about, but let me try to explain as best I can. "Gain" invariably means "small signal voltage gain" (output signal voltage / input signal voltage). The fact that a MOSFET gate allows no DC current isn't relevant (though its true). The job of analog circuits is to handle small signals.

Suppose a transistor is being used for amplification in an analog circuit, it is "DC biased" to put it in the high gain regime. A small signal voltage is applied between gate and source (or between base and emitter), creating a small signal current from drain to source (or from collector to emitter). The ratio of this small signal current to the small signal voltage is called "transconductance." My sense is that BJTs have substantially higher transconductance than MOSFETs. For a tiny bit of support, see http://www-inst.eecs.berkeley.edu/~ee130/SP03/homework/hw13soln.pdf. This small signal current may drive a resistive load, giving an small signal output voltage of the current times the resistance of the load. Thus you end up with a higher "gain" (output voltage/input voltage).

I'm really shaky on everything analog, and that's why I made such a vague statement. I just felt like it would be inappropriate to only talk about digital stuff when analog circuits are very important. I think what I wrote is essentially correct, but if someone wants to delete it that's fine. I'd rather someone teach me though! Rmalloy 00:42, 16 Jul 2004 (UTC)

The gain issue is easily misinterpreted and is always good to start a flame war at news://sci.electronics.* or http://www.diyaudio.com. I'd write something into article but for the fear of a edit war! In essence there are four quantities which can be seen as geen dV(out)/dV(in), dI(out)/dV(in), dV(out)/dI(in), and dI(out)/dI(in). Of course MOSFET score big on dV(out)/dI(in) and dI(out)/dI(in) in NF, as no input current flows, but the practical significance is more that there is moe leeway in designing the preceeding stage.

What's more the problem with MOSFETs in discrete designs, is the variabiliy of there threshold voltage.

Pjacobi 07:27, 16 Jul 2004 (UTC)

It's not true that no *small signal* input current flows into a MOSFET. Current is constantly charging and discharging the MOSFET gate, so dI(in) != 0. In fact, capacitors, like the MOS capacitor, are short-circuits to high-frequency current. I think this topic is probably best left alone in the article unless someone is an expert on the subject, so we avoid misinformation.Rmalloy 13:04, 16 Jul 2004 (UTC)

Agreed that the transconductance of a BJT is favorable compared to a MOSFET. I'll made the change in the article. Thanks, Glengarry 14:56, 16 Jul 2004 (UTC)

[edit] basic circuits

each basic circuit needs an article. common source, common drain, common gate, source follower amplifiers, etc. i can, of course, draw schematics. but i don't know these well enough to do the articles. i can start them with what i know... same for BJTs. - Omegatron 16:00, Jan 19, 2005 (UTC)

[edit] BJTs as voltage controlled resistors

I ve not heard this one before. So we can all now use BJTs instead of FETs to create a voltage controlled resistor. I dont think so! Statement needs modifying/removing cos its wrong. Light current 04:11, 17 August 2005 (UTC)

Saying "wrong" loudly doesn't help. You have to say why it's wrong. In fact it's not wrong: the current in any diode is controlled by the width of the depletion layer, and this width is controlled by the voltage across the diode. The same applies to BJT transistors: the BE voltage determines the width of the depletion layer in the BE junction, and this layer controls both the base current and the emitter current. Yes, the collector current is proportional to the base current. But if you believe that the base current can directly control the collector current, then you don't understand how BJT transistors actually work. The simple transistor equation is Ic = hfe * Ib, but this hides the physics behind the BJT operation. The full-blown Eber-Molls transistor equations show what's happening: Both Ib and Ic are mostly determined by Vbe. --Wjbeaty 00:17, August 19, 2005 (UTC)

All Im saying is that a BJT is NOT a voltage controlled resistor (because of the high impedance at the collector) as the article initially implied. Light current 00:23, 19 August 2005 (UTC)

OK, but then the same reasoning says that FETs aren't voltage-controlled resistors either. Both BJTs and FETs are voltage-controlled current sources. --Wjbeaty 00:34, August 19, 2005 (UTC)

No, I dont agree. FETs appear totally resistive near the origin (below pinch off), thats why they can be used as VCRs. In fact Siliconix made aspecial range of FETs for this very purpose (VCR2N, VCR3P, VCR4N, VCR5P,VCR6P,VCR7N). Are you saying that BJTs can give as good a perfomance as FETs in this region??Light current 00:55, 19 August 2005 (UTC)

Agree that FETs are not VCRs when pinched off. I've altered staement in article. See if you agree with it.Light current 01:16, 19 August 2005 (UTC)

Besides, it says "can be thought of":

"FETs, like all transistors, can be thought of as voltage-controlled resistors."

As a teaching aid for someone completely new to transistors, this is a good analogy, and is used often:

• The Rheostat as a Transistor
• The Field Effect Transistor as a Voltage Controlled Resistor
• [2]

Much better than telling them it's an "amplifier". We can certainly change it to say "as a very rough first approximation" or something. - Omegatron 22:52, August 21, 2005 (UTC)

I think saying 'voltage controlled resistor' can be confusing to the newcomer (and more experienced people) because it gives the impression that the transistor collector looks like a resistor when in fact it looks like a current source/sink. I think we should say 'all transistors act as voltage controlled current sources' (as User:Wjbeaty has suggessted).Light current 17:11, 24 August 2005 (UTC)

Are you guys saying that a bipolar transistor is a voltage-controlled device? That’s wrong they are current controlled. Small base current change gives large collector current change. The FET is a voltage-controlled device. Which I like using in my projects because they are the closest things to tubes, which I cut my wisdom teeth on in the late 60's early 70's. Inkdoe 13:22, 20 October 2005

What about MFET ? Magnetic Field effect transistors, and spintronic ?

What about them? If you know about these devices, please feel free to add material on them. :-) Light current 11:53, 28 August 2005 (UTC)

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moved from page;

" Field Effect Transistor (FET) patented in 1934 by Dr. Oskar Heil. Personally first read about the FET patent year in Analog Science Fiction Science Fact magazine in the late 70s early 80s in an article about hearing aides by Larry Niven or Jerry Pournelle."

[edit] Errors ID'd by Nature, to correct

The results of what exactly Nature suggested should be corrected is out... italicize each bullet point once you make the correction. -- user:zanimum

• In the section on USES, CMOS is the acronym for Complementary Metal Oxide Semiconductor.
• The first sentence of the section “FET Operation” mentions a “potential voltage” which is misleading. In electrical terminology “potential” and “voltage” tend to mean the same and hence both are not normally used together. It is best to use the word VOLTAGE alone for the purposes of describing how the FET works.
• There are many types of FET but the section on FET Operation describes a “normally-on” or “depletion mode” type of MOSFET. However, it is usual to employ a “normally-off” MOSFET for CMOS devices which are described in the section on USES.

[edit] Behavior of d mode FETs

Near the top, the article says "depletion, in which a voltage applied decreases the current flow from source to drain." This isn't true, is it? I think whoever wrote that sentence was confusing the difference between n-channel and p-channel, with the difference between enhancement mode and depletion mode. It would be more accurate to say "enhancement mode, which is normally off, when zero voltage is applied, and depletion mode, which is normally on, when zero voltage is applied." Objections to this change? --Monguin61 17:55, 4 March 2006 (UTC)

It's true depending on what definitions are used, but it's definitely not clear. It's hard to make things both accurate and accessible. How do you define "when zero voltage is applied" without making things too complicated? - mako 03:30, 5 March 2006 (UTC)

I think "normally off" and "normally on" should suffice. That's more towards the accessible side than accurate, but more accurate than the current phrasing, yes? --66.253.212.165 08:09, 7 March 2006 (UTC)

[edit] What's the difference between an NPN transistor and a FET?

I was wondering what the difference between an NPN transistor used in TTL logic for example, and a(n) FET transistor?

Do they not both work by applying a small current to the base to all a current to pass through?

So what are the differences between the construction/operation of an NPN transistor and a(n) FET transistor?

This page didn't really give me much help on the construction of a(n) FET transistor, as from what I see it looks EXACTLY the same as an NPN transistor. And from what I can see it works the same way too, except somehow uses energy mostly when switching states instead of during. How is it that it uses less energy than an NPN transistor?

What are the main differences between a(n) FET transistor and an NPN transistor?

How is it that an NPN transistor uses up more energy than a(n) FET transistor?

How is it that a(n) FET transistor has to be used differently for logic gates than an NPN transistor?

Thanks so much for your help! --TAz69x 23:50, 16 April 2006 (UTC)

basically, a FET is a voltage-controlled device, whereas a bipolar transistor^(NPN or PNP) is current-controlled. A good explanation of the operating principle of one of the FETs is given in the JFET article. A FET is a majority carrier device. There is no need to inject carriers to modify the behaviour of a zone, like with the bipolar transistor (which is a minority carrier device). Instead, in a FET, we use an electric field to attract or repel charges that are already present in the material.

It is difficult to tell what are the difference in construction with a bipolar, because the FET family is quite large. Compare the cross sections in the JFET, MOSFET, bipolar transistor articles. FET use less energy than bipolar because they absorb almost no current when in the on-state. The input of a FET can be seen as a capacitor: you only need to supply current to charge the capacitor. You don't have to supply energy once the capacitor is charged! The input of a bipolar transistor is like a diode: once you reach the threshold voltage of the diode, current starts to flow, so you have to supply energy to bias the diode.

Concerning the use of FET in logic, I think you should have a look at the CMOS article. Hope it helps -- CyrilB 08:46, 17 April 2006 (UTC)

[edit] Field Effect Transistors as Light Detectors

I have recently been investigating the process by which a PIN diode can modulate a signal as a result of incident radiation. My main point of confusion has been my inability to find any mechanical diagrams of a PIN diode which operates through the presence of 3 terminals. Most of what I have read suggests that this is a strictly 2-terminal device (the PIN in question, a Hamamatsu S5971). I came across a diagram for a FET, and was struck by not only the presence of the proper number of terminals, but the drain signal's dependence on variations in the space charge region. I am mainly curious as to the possibility that my PIN may be closer in design to an FET, through the use of the intrinsic region as the source of the drain terminal. Whether this is may be a step in the proper direction or its equally likely counterpart, I would appreciate any insight that may be offered on the subject. Jmeyers 18:39, 10 May 2006 (UTC)

I don't know of any similarity between a PiN diode and a FET. A PIN diode is a two terminal device, operated in reverse bias. Light on the diode causes carrier generation which effectively looks like a leakage current proportional to the light on the PIN diode. Even a PN junction diode does this, the largish I (intrinsic) portion just increases the area where generation occurs making it more sensitive to light. Maybe the charge coupled device is what you have in mind as a three terminal device, or a phototransistor. Snafflekid 23:34, 10 May 2006 (UTC)

[edit] Pinch off description... wrong or misleading!!

It costed 2 days of research, but i finally find out that the confusion in my head came from your description of the pinch-off mode. In your description you talk about the "saturation" area, where increasing source voltage you don't have corresponding increase of drain current and you call it pinch-off ... but still there is current and its value depend on the value of the gate voltage. While the pinch-off voltage is the value of the GATE voltage for which there is no drain current at all, for any value of source-to-drain voltage (even in the ohmic region!).

see reference: http://www.st-andrews.ac.uk/~jcgl/Scots_Guide/info/comp/active/jfet/jfetchar/jfetchar.htm

152.78.72.52 20:03, 3 February 2007 (UTC)

Hm? When the channel pinches off, that doesn't imply zero current flow at all, it merely makes the drain current a much weaker function of drain voltage (until you apply sufficient bias to trigger a breakdown mechanism). This is because the pinched off (spacial) area is a depletion region. Most of the applied bias beyond the saturation (pinch-off) voltage is dropped over this depletion region, thus it contains a large internal electric field that can sweep carriers from one side to the other (so current still has a path to flow). Since bias beyond Vsat is dropped over the depletion region rather than the channel, the S-D current no longer changes very much with the drain voltage, so the drain current stays relatively constant beyond the pinch-off point; the so-called "saturation region". Of course the current still does increase slightly with increasing drain voltage, and this is mostly due to channel length modulation (additional bias expands the depletion region and thereby shortens the channel). Admittedly, the explanation in the article is a little confusing, but it seems accurate.

If you're really interested in learning this stuff, pick up a book on semiconductor devices and physics. You won't get a good intuition for how devices work just from reading a Wikipedia article. The Pierret, Sze, and Neaman books are all pretty good. -- mattb @ 2007-02-03T21:22Z

Ok... looking around for even longer i solved my doubts, i just want to leave the observation for others: the pinch off point is indeed what you describe. In particular, for Vgate=0 is the value of Vsource=Vpo when the saturation start (the channel is "almost close"). But on the other side if Vgate=Vpo, the channel is already almost close by the bias of the gate, so the drain current "saturate" soon, for very small value, and stay almost zero for any value of Vsource. That's why it can be seen in a transconductance graph as the value of Vgate for Idrain=0. Am I right?