SDRAM
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SDRAM means synchronous dynamic random access memory which is a type of solid state computer memory.
Other dynamic random access memories (DRAM) have an asynchronous interface which means that it reacts as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to its control inputs. It is synchronized with the computer's system bus, and thus with the processor. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than DRAM which does not have synchronizing control circuits.
Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears a fixed number of clock pulses after the read instruction. This delay is called the latency and is an important parameter to be considered when purchasing SDRAM for your computer. It is not necessary to wait for the data to appear before sending the next instruction.
SDRAM chips are rated according to their maximum clock rate and their read cycle time. Clock rate is directly proportional to maximum bandwidth and is affected primarily by the speed of the internal state machine and interface circuitry. Read cycle time affects the delay between issuing a command and initiating the corresponding operation and is determined primarily by the speed of the memory cells themselves.
SDRAM modules are typically rated according to their maximum clock rate (which may differ from that of the chips on the module) and by their CAS latency. CAS latency is the delay between specifying a column address and receiving the first data output and is closely related to read cycle time. It is specified in clock cycles, typically with the assumption that the module is running at its maximum speed. However, CAS latency is actually programmable by the memory controller, and a lower CAS latency setting may be viable if the module is running slower than its rated clock speed. When 100 MHz SDRAM chips first appeared, some manufacturers sold modules that could not reliably operate at that speed. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential; the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (although the actual meaning of the numbers varies widely among different types of modules).
Although the concept of synchronous DRAM has been known since at least the 1970s and was used with early Intel processors, it was only in 1993 that SDRAM began its path to universal acceptance in the electronics industry. In 1993, Samsung's introduced its KM48SL2000 synchronous DRAM, and by 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater speed.
SDRAM latency is not inherently lower than asychronous DRAM; indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.
Today, virtually all SDRAM world-wide is manufactured compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR and DDR2 SDRAM.
SDRAM is also available in registered memory varieties, for systems that need greater scalability.
Currently, 168-pin SDRAM type is not used in new PC systems, and PCs come with DDR or DDR2 SDRAM, with DDR2 quickly superseding DDR.
Today, the world's largest manufactures of SDRAM include: Samsung Electronics, Micron Technology, Qimonda (formerly Infineon Technologies) and Hynix.
[edit] SDR SDRAM
Originally simply known as "SDRAM", Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 (ECC) bits at a time.
All commands timed relative to the rising edge of a clock signal. In addition to the clock, there are 6 control signals, mostly active-low, which are sampled on the rising edge of the clock:
- CKE Clock Enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high.
- /CS Chip Select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
- DQM Data Mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
- /RAS Row Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /CAS and /WE, this selects one of 8 commands.
- /CAS Column Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /RAS and /WE, this selects one of 8 commands.
- /WE Write enable. Along with /RAS and /WE, this selects one of 8 commands. This generally distinguishes read-like commands from write-like commands.
SDRAM devices are internally divided into 2 or 4 independent internal banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands understood are as follows.
| /CS | /RAS | /CAS | /WE | BAn | A10 | An | Command |
|---|---|---|---|---|---|---|---|
| H | x | x | x | x | x | x | Command inhibit (No operation) |
| L | H | H | H | x | x | x | No operation |
| L | H | H | L | x | x | x | Burst Terminate: stop a burst read or burst write in progress. |
| L | H | L | H | bank | L | column | Read: Read a burst of data from the currently active row. |
| L | H | L | H | bank | H | column | Read with auto precharge: As above, and precharge (close row) when done. |
| L | H | L | L | bank | L | column | Write: Write a burst of data to the currently active row. |
| L | H | L | L | bank | H | column | Write with auto precharge: As above, and precharge (close row) when done. |
| L | L | H | H | bank | row | Active: open a row for I/O. | |
| L | L | H | L | bank | L | x | Precharge: Deactivate current row of selected bank. |
| L | L | H | L | x | H | x | Precharge all: Deactivate current row of all banks. |
| L | L | L | H | x | x | x | Auto refresh: Refresh one row of each bank, using an internal counter. All banks must be precharged. |
| L | L | L | L | 0 0 | mode | Load mode register: A0 through A9 are loaded to configure the DRAM chip. The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles) | |
Use of the data bus is intricate and requires a complex DRAM controller. This is because data written to the DRAM must be presented in the same cycle as a write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.
Typical SDR SDRAM clock speeds are 66, 100, and 133 MHz (15, 10, and 7.5 ns/cycle). Speeds up to 150 MHz are available for a price.
[edit] DDR SDRAM
While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a Double Data Rate interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. Some minor changes to the SDR interface timing were made in hindsight.
DDR SDRAM doubles the minimum read or write unit; every access refers to at least two consecutive words.
Typical DDR SDRAM clock speeds are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMS are known as PC2100, PC2700 and PC3200. Speeds up to DDR-550 (PC4400) are available for a price.
[edit] DDR2 SDRAM
DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to 4 consecutive words. The bus protocol was also simplified to allow higher speed operation. (In particular, the "burst terminate" command is deleted.) This allows the bus speed of the SDRAM to be doubled without increasing the speed of internal RAM operations; instead, internal operations are performed in units 4 times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow 8 banks on large RAM chips.
Typical DDR2 SDRAM clock speeds are 200, 266, 333 or 400 MHz (5, 3.75, 3 and 2.5 ns/cycle), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (2.5, 1/875, 1.5 and 1.5 ns per beat). Corresponding 240-pin DIMMS are known as PC2-3200 through PC2-6400. Speeds up to DDR2-1250 (PC2-10000) are available for a price.
Note that because internal operations are at 1/2 the clock rate. DDR2-400 memory (internal clock speed 100 MHz) has somewhat higher latency than DDR-400 (internal clock speed 200 MHz).
[edit] DDR3 SDRAM
DDR3 continues the trend, doubling the minimum read or write unit to 8 consecutive words. This allows another doubling of bandwidth and external bus speed without having to change the speed of internal operations, just the width.
(Actually, DDR3 supports "burst chop" operation[1] where bursts of only 4 words appear on the data bus. However, this requires the same amount of time internally as an 8-word burst.
DDR3 memory chips are being made commercially[2], but computer systems able to use them are not expected until late 2007[3], with significant usage in 2008.[4][5]. Initial speeds are 400 and 533 MHz, which would be described as DDR3-800 and DDR3-1066, but speeds of 667 and 800 MHz (DDR3-1333 and DDR3-1600) are expected in time.[6] This high speed poses a significant engineering challenge, so the 2008 schedule may be optimistic.[7]
[edit] See also
- Random access memory (RAM)
- SDRAM latency
- Static RAM (SRAM)
- Non-Volatile RAM (NVRAM)
