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IA-64 - Wikipedia, the free encyclopedia

IA-64

From Wikipedia, the free encyclopedia

In computing, IA-64 (short for Intel Architecture-64) is a 64-bit processor architecture developed cooperatively by Intel Corporation and Hewlett-Packard (HP), and implemented in the Itanium and Itanium 2 processors. The goal of IA-64 was to produce a "post-RISC era" architecture that would address some of the key challenges faced by older architectures, to enable more efficient performance scaling in future processor designs. IA-64 is a completely separate architecture from Intel 64 and from all other variants of x86-64.

The IA-64 architecture was built around a computing model called Explicitly Parallel Instruction Computing (EPIC). EPIC was designed to increase the ability of microprocessors to execute software instructions in parallel by using the software compiler—rather than complex logic circuits on the processor itself—to identify and leverage opportunities for parallel execution. With this approach, Intel and HP hoped to drive performance gains by increasing the amount of work that could be accomplished during each processor clock cycle.

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[edit] Background: Instruction Level Parallelism

EPIC was not the first attempt to increase parallel throughput for software code. In a mainstream "out-of-order" processor design, a complex decoder system examines each software instruction as it flows through the pipeline and determines which instructions can be safely executed in parallel using the available execution units. For example, the instructions A = B + C and D = F + G have no effect on each other, so they can be executed simultaneously. The ability to identify and exploit such opportunities for parallel execution is called instruction level parallelism (ILP), and is essential for good performance in modern CPUs.

Predicting which instructions can and cannot be executed in parallel is a very complex task. In many cases the execution of one stream of instructions depends on the output of another, but only if some third condition is true. For instance, consider this slight modification of the example noted above: A = B + C; IF A=5 THEN D = F + G. In this case, the result of the first calculation must be known in order to determine if the second calculation should be executed at all.

In such cases the circuitry on the CPU typically "guesses" what the result of the first calculation will be, a process known as branch prediction. In something like 90% of all software code, an IF statement can be assumed true,[citation needed] so that in our example, the second half of the command can probably be safely executed in parallel with the first command. However, a wrong guess can cause a significant performance hit, because the result has to be thrown out, and the CPU has to reprocess the second instruction.

Improvements in prediction logic have played a critical role in increasing the performance of modern CPUs. In recent years, however, branch prediction accuracy in Intel architectures has reached levels in excess of 98%. At such levels, the cost and complexity of further improvement increases rapidly, requiring ever-more development effort, CPU die space, and manufacturing resources. Because of the rising expense and diminishing returns, further improvements in hardware-based branch prediction are no longer seen as a meaningful strategy for increasing processor performance.

[edit] Explicitly parallel instruction computing

With EPIC, IA-64 takes a different approach to instruction level parallelism, relying on the software compiler rather than CPU logic circuits to identify and capitalize on opportunities for parallel throughput. Even before the program is fed into the CPU, the compiler examines the code and makes the same sorts of decisions that would otherwise happen at "run time" on the chip itself. Once it has decided which paths to take through the code, it gathers up the instructions it knows can be run in parallel, bundles them into larger instructions, and then stores them in that form in the program—hence the name VLIW or "very long instruction word."

Moving this task from the CPU to the compiler has several advantages. First, unlike traditional branch prediction, compilation does not take place during runtime. The compiler can therefore spend considerably more time examining the code to find additional opportunities for parallel throughput and increase branch prediction accuracy. Second, offloading prediction to the compiler eliminates the need for branch prediction circuits, which are enormously complex. The CPU no longer has to examine anything; it simply breaks the instruction apart again and feeds the pieces into the appropriate execution units. Third, doing branch prediction in the compiler is a one-off cost, whereas runtime branch prediction must be performed every time the program is run.

The downside of this compiler-based approach is that it is not always easy to predict a program's runtime behavior. In a traditional design, the CPU can make decisions on the basis of actual run-time data which the compiler can only guess at. Because of this limitation, it is possible for the compiler to get its predictions wrong more often than comparable (or simpler) runtime logic circuits. The EPIC design thus relies heavily on the performance of the compilers, and reduces hardware complexity in exchange for a somewhat greater increase in software complexity.

[edit] IA-64 Architectural Details

[edit] Registers

To enable very fast throughput of multiple, independent instructions, the IA-64 architecture includes a very generous complement of registers, including 128 82-bit floating point registers, and an equal number of 64-bit integer registers. In addition to the sheer number of registers, IA-64 includes a register rotation mechanism that is controlled by the Register Stack Engine. Rather than the typical spill/fill or window mechanisms used in other processors, the IA-64 processor can rotate in a set of new registers to accommodate for new function parameters or temporaries. The register rotation mechanism combined with predication is also very effective in executing automatically unrolled loops.

[edit] Instruction set

IA-64 also provides instructions for multimedia operations and floating point operations. Where a typical VLIW will assign sub-instructions from each long instruction word to a particular fixed functional unit, IA-64 supports several bundle mappings to allow for more instruction mixing possibilities and to provide a balance between serial and parallel execution modes. There was room left in the initial bundle encodings to add more mappings in future versions of IA-64. In addition, the IA-64 has individually settable predicate registers to issue a kind of runtime-determined "cancel this command" directive to the respective instruction. This is sometimes more efficient than branching.

[edit] Pre-OS and runtime sub-OS functionality

When first booted an IA-64 processor is missing some of its instruction functionality. A "Processor Abstraction Layer" (PAL) is integrated into the system BIOS. At boot time, the PAL is loaded into the CPU to provide a low-level interface that abstracts some instructions and provide a mechanism for processor updates distributed via a BIOS update. During BIOS initialization an additional layer of code, the "System Abstraction Layer" (SAL) is loaded that provides a uniform API for implementation-specific platform functions.

On top of the PAL/SAL interface sits the "Extensible Firmware Interface" (EFI). EFI is not part of the IA-64 architecture, but by convention is required on all IA-64 systems. It is a simple API for access to logical aspects of the system (storage, display, keyboard, etc), and is combined with a lightweight runtime environment (similar to DOS) that allows basic system administration tasks such as flashing BIOS, configuring storage adapters, and running an OS boot-loader.

Once the OS has been booted, some aspects of the PAL/SAL/EFI stack remain resident in memory and can be accessed by the OS to perform low-level tasks that are implementation-dependent on the underlying hardware.

[edit] IA-32 support

The original IA-64 architecture included support for IA-32 instructions and could therefore run the many thousands of applications available for x86-based systems. This can eliminate the added expense and complexity of deploying a second server or porting code from IA-32 to IA-64. However, performance was slower than for native IA-64 code and about 50% slower than for the same IA-32 code running on x86 servers of the time.

Although succeeding implementations of the architecture improved the IA-32 performance, Intel introduced a software emulation scheme that proved to be more effective and released it in 2004. Starting with the Montecito processor in July 2006, newer implementations no longer directly support the IA-32 instruction set. The emulator must be integrated with the OS. The Windows emulator is available from Microsoft. The Linux emulator is available from Linux vendors such as Novell and Red Hat, and from Intel itself.

[edit] Software support

IA-64 is currently supported by approximately 10 operating systems,[1] including OpenVMS, Windows and various versions of Linux and UNIX, and there are more than 10,000 applications now available that run natively on the platform (as of October, 2006)[2]. The lack of software was initially seen as a serious shortcoming of the architecture.

In the commercial arena, software support is generally strongest for data-tier applications (database, data warehousing and business intelligence), and for large-scale enterprise transactional applications (such as enterprise resource planning and customer relationship management). In high-performance and technical computing, support is strongest for applications that rely on very large datasets and for workloads that are not easily distributed across multiple, smaller servers. (A list of Itanium applications is available on the Itanium Solutions Alliance Web site). HP maintains its own application lists.

  • HP's UNIX operating system, HP-UX, has been available on IA-64 since the Itanium introduction in 2001. OpenVMS[3] support was added in June, 2003. The HP NonStop operating system also runs on IA-64. NonStop is a family of fault-tolerant servers that are used in many of the world's trading and financial markets.
  • FreeBSD has supported IA-64 systems since release 5.0. IA-64 support in NetBSD is currently (as of 2006) under development.
  • Sun developed a port of Solaris for IA-64, but abandoned the effort in 2000[4]. However, Transitive has released binary translation software that enables Sun Solaris applications to run on IA-64 Linux servers “without any source code or binary changes.” According to the company, with their software, computational performance for Solaris applications on IA-64 systems is “faster than the fastest SPARC server.”[5]
  • IBM worked with SCO to port AIX to the Itanium processor as part of Project Monterey but this was never officially released "since continued delays in production availability of Itanium systems eroded the enthusiasm and critical solution support of partners and ISVs, while industry focus shifted toward the substantial growth and momentum of Linux on 32-bit Intel systems." [6] However, IBM has ported DB2 and many IBM middleware applications to IA-64 running HP-UX, and, according to an HP press release, porting efforts have accelerated as of 2006.
  • An IA-64 port of Tru64 UNIX was developed by Compaq [8], but canceled after HP's acquisition.

[edit] IA-64 based Solutions

[edit] 3D Animation and Rendering

Although there were early moves to port some 3D animation products such as Maya to IA-64 [9], the arrival of x86-64 systems proved a more attractive proposition for ISVs in this market with the benefit of backward compatibility for their existing x86 versions, and most IA64 porting efforts were discontinued.

[edit] Market trends

IDC reported that from its release in 2001 until September 2005, 70,000 Itanium systems were deployed, representing $3 billion in sales.[10] Others pointed out that much of the market growth was the result of HP customers transitioning from PA-RISC to Itanium, and did not indicate broad market acceptance. Some of Itanium’s more emphatic detractors refer to Itanium as “Itanic” and continue to speak of the demise of the architecture, but Intel and HP are “bullish on Itanium.” [11]. IDC released a report noting a high level of satisfaction among Itanium adopters [12].

The hardware vendors of the Itanium Solutions Alliance have committed to investing a collective $10 billion in the architecture through the end of the decade, and the Alliance reports that the total revenue for Itanium solutions as of January 2006 represented approximately 58 percent of total revenue for Sun’s SPARC architecture and approximately 33 percent of total revenue for IBM’s Power 2 architecture: [13] in simpler terms, IA-64 system revenue then represented about 17% of the combined system revenue for IA-64, SPARC, and POWER 2 systems.

A number of notable startups have entered the market as of 2006. One developed a small operating system kernel designed to run beneath other popular operating systems (Linux, Windows, etc.). This kernel takes advantage of some of Itanium's unique capabilities (protection ID's and compartments) in an attempt to increase both security and performance. Another provides Itanium-based systems that are compatible with IBM’s mainframe operating environment, and can run the IBM z/OS operating system, as well as Windows and Linux. The success of these products in the marketplace is yet to be determined.

[edit] Technical strengths

The Intel Itanium architecture.
The Intel Itanium architecture.

IA-64 was specifically designed to provide a very high level of parallel processing, to enable high performance without requiring very high clock frequencies (which can lead to excessive power consumption and heat generation). Key strengths of the IA-64 architecture include:

  • Up to 6 instructions/cycle: The processor can handle up to 6 simultaneous 64-bit instructions per clock cycle, and the dual-core version can support up to two software threads per core.
  • Extensive execution resources per core: 256 application registers (128 general purpose, 128 floating point) and 64 predicate registers.
  • Large cache: 24 MiB in the dual-core version (12 MiB per core), providing data to each core at up to 48 GiB/s.
  • Large address space: 50-bit physical / 64-bit virtual.
  • Small, energy-efficient core: Since IA-64 relies on the compiler for scheduling instructions for parallel throughput (other architectures rely on runtime optimization within the processor itself), it has fewer transistors in each core. This may be an advantage in current and future multi-core designs. [14]

For specific architectural details of the most recent IA-64 processor, see the article on Montecito.

[edit] Competing architectures

Although other 64-bit architectures have existed for a long time, Hewlett Packard has retired the Alpha and PA-RISC architectures in favor of IA-64. SGI planned to retire the MIPS in favor of IA-64, but was forced to create additional generations as Itanium deliveries were delayed. The 64-bit MIPS architecture is still in production by other manufacturers, but primarily in niche applications.

AMD's AMD64 architecture, first delivered in 2003, found success in the marketplace, the Itanium was delayed, and Intel decided to implement the AMD64 architecture under its own name EM64T (now called Intel64). The AMD64/Intel64 architecture is a 64-bit upgrade to the x86 architecture. AMD64/Intel64 is often referred to generically as the "x86-64 architecture".

As of 2006, Itanium's competition for the 64-bit server market appears to be IBM's POWER architecture, Sun's UltraSPARC architecture, and x86-64.

[edit] See also

[edit] External links

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