Partial re-configuration
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Partial re-configuration is the process of configuring a portion of a field programmable gate array while the other part is still running/operating.
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Hardware, like software, can be designed modularly, by creating subcomponents and then higher-level components to instantiate them. In many cases it is useful to be able to swap out one or several of these subcomponents while the FPGA is still operating.
Normally, reconfiguring an FPGA requires it to be held in reset while an external controller reloads a design onto it. Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a reconfigurable module. Partial reconfiguration also can be used to save space for multiple designs by only storing the partial designs that change between designs.
A common example for when partial reconfiguration would be useful is the case of a communication device. If the device is controlling multiple connections, some of which require encryption, it would be useful to be able to load different encryption cores without bringing the whole controller down.
Partial reconfiguration is not supported on all FPGAs. In current versions of software, Xilinx supports partial reconfiguration on Virtex II, Virtex II Pro, and Virtex 4 FPGA lines. A special software flow with emphasis on modular design is required. Typically the design modules are built along well defined boundaries inside the FPGA that require the design to be specially mapped to the internal hardware.
Note: Partial Reconfiguration is only the update of a portion of the FPGA, it does not require that any portion of the FPGA continue running during the update. Xilinx refers to reconfiguring a portion of the FGPA while the remainder continues to run by the term "partial dynamic reconfiguration".
