Principle of logical effort
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The principle of logical effort is a guideline in VLSI design to determine the preferred design of several that implement a logical statement - it states that the design with the minimum propagation delay is preferred.
This comparison involves
- the logical effort
- the electrical effort, defined as the ratio of capacitance at the output of a logic gate compared to the capacitance of the input (where the capacitance is directly proportional to the width of the CMOS gate)
- the branching effort, or any delay that results from the path chosen between gates
- the parasitic delay resulting from parasitic capacitance (which is usually small and can be ignored)
These values are calculated for inverters (designed using static CMOS logic) and the values for other logic gates are defined in terms of this value.
Capacitance is directly proportional to the width of the CMOS gate.
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