Backside bus
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In computer microprocessor architecture, a backside bus is a bus dedicated to the purpose of connecting the processor to an off-chip bank of cache memory. This is an improvement over the older practice of accessing the cache over the frontside bus (FSB) because it reduces the usage of the FSB, which is typically a severe bottleneck in most modern systems. Furthermore, since the backside bus operates over a shorter distance, it can typically operate at higher clock speeds, allowing higher bandwidth access to the cache.
This architecture has been used in a number of chips, including the Intel Pentium Pro and Pentium II processors (which used it for access to their L2 cache; earlier processors had accessed the L2 cache over the FSB, while later processors moved it on-chip) and IBM's PowerPC (the G3 line, certain PowerPC 604 models (codename Mach5) and some chips of the G4 line).
[edit] References
- Monday a big day for Apple. CNet (7 November 1997).
- Buses: frontside and backside. ITworld.com (30 April 2001).
[edit] External links
- Backside Bus at Whatis.com
- Dedicated Backside Cache Bus at PCGuide.Com
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