Configware Compiler

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A Configware Compiler is used in the area of Reconfigurable Computing for data-stream-based reconfigurable systems using platforms like FPGAs or coarse-grained reconfigurable datapath arrays (rDPAs) to generate two different blocks of code: configware code and flowware code (see figure). By placement and routing the mapper generates the configware code for reconfiguration of the platform. Based on the mapper's result the data scheduler generates the flowware code which is used to organize the data streams needed by programming the data counters through reconfiguration of the address generators, such as for instance Generic address generators GAG, in the Auto-sequencing memory (ASM) blocks. A configware compiler may be, for instance, part of a Configware/Software Co-Compiler.

The fundamental architectural model behind this methodology is the Super systolic array (KressArray), a generalization of the systolic array having been derived by Rainer Kress, who replaced the algebraic synthesis models known from original systolic arrays restricting their use only to applications with regular data dependencies, by simulated annealing merging both the mapper and the data scheduler.

[edit] External links

• Generalization of the systolic array