Frequency divider
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A frequency divider is an electronic circuit that takes an input signal with a frequency, fin, and generates an output signal with a frequency:
where n is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.
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[edit] Analog dividers
[edit] Regenerative frequency divider
A regenerative frequency divider, also known as a Miller frequency divider,[1] mixes the input signal with the feedback signal from the mixer.
The feedback signal is fin / 2. This produces sum and difference frequencies fin / 2, 3fin / 2 at the output of the mixer. A low pass filter removes the higher frequency and the fin / 2 frequency is amplified and fed back into mixer.
Steady state examination seems simple enough however startup is more complicated. In order to establish a stable 1/2 frequency feedback, the amplifier gain at the half frequency must be greater than unity. The phase shift must also be an integer multiple of 2pi.
[edit] Injection-locked frequency divider
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[edit] Digital dividers
To divide a digital signal by an integer multiple a Johnson counter is used. This is a type of shift register network that is clocked by the input signal. The last register's complemented output is fed back to the first register's input. The output signal is derived from the combination of the register outputs. For example, a divide-by-3 divider can be constructed with a 3-register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the network is clocked by the input signal. The values 000 and 111 occur three clock pulses apart and control the state change of the output signal. Additional registers can be added to provide additional integer divisors.
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the rate, the third bit is 1/4 the rate, etc.
[edit] Fractional-n dividers
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.
[edit] Delta-sigma fractional-n synthesizers
If the sequence of divide by n and divide by (n + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of n and (n + 1), while maintaining the time-averaged ratios.
[edit] See also
[edit] References
- ^ R. L. Miller (1939). "Fractional Frequency Generators Utilizing Regenerative Modulation". Proceedings of The IRE: 446–457.
