Quad Data Rate SRAM
From Wikipedia, the free encyclopedia
Quad Data Rate (QDR) SRAM is a type of static RAM computer memory that can transfer up to four words of data in each clock cycle. Like Double Data-Rate (DDR) SDRAM, QDR SRAM transfers data on both rising and falling edges of the clock signal. This requires more wires between the memory device and the memory controller, but doubles the theoretical maximum data transfer rate. QDR SRAM uses two clocks, one for read data and one for write data. This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows concurrent reads and writes, thereby doubling the transfer rate again.
QDR SRAM is designed for high-speed communications and networking applications, where data throughput is more important than cost, power efficiency or density. The technology is a joint development by Cypress, Renesas, IDT, NEC, and Samsung.
Contents |
[edit] I/O
[edit] Clock inputs
4 clock lines:
- Input clock:
- K
- not-K, or /K
- Output clock:
- C
- not-C, or /C
[edit] Control inputs
Two control lines:
- not-Write enable: /WPS
- not-Read enable: /RPS
[edit] Buses
One address bus and two data buses:
- Address bus
- Data in bus
- Data out bus
[edit] Clocking scheme
- Addresses
- Read address latched on rising edge of K
- Write address latched on rising edge of K
- Data
- Write
- If /WPS is low
- A data word on Data In is latched on rising edge of K
- The next data word on Data In is latched on rising edge of /K
- If /WPS is low
- Read
- A read is a two-cycle process
- If /RPS is low
- The first rising edge of K latches the read address, A
- The second rising edge of K puts the data word, from address A, on the Data Out bus
- The next rising edge of /K puts the next data word, from address A+1, on the Data Out bus
- Write
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[edit] External Links
- QDR SRAM home page
- Quad Data Rate SRAM Clocking Scheme Cypress
- Quad Data Rate Description Electronic design article
