Hardware description language

From Wikipedia, the free encyclopedia

In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.

An HDL is a standard text-based expression of the temporal behaviour and/or (spatial) circuit structure of an electronic system. In contrast to a software programming language, an HDL's syntax and semantics include explicit notations for expressing time and concurrency which are the primary attributes of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages.

HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives the illusion of HDLs being a programming language. Simulators capabable of supporting discrete event (digital), and continuous time (analog) modeling exist and HDLs targeted for each are available.

It is certainly possible to represent hardware semantics using traditional programming languages such as C++ (and augmented with extensive and unwieldy class libraries.) However, the C++ language does not include any capability for expressing time explicitly and consequently is not a proper hardware description language.

Using the proper subset of virtually any (hardware description or software programming) language, a software program called a synthesizer can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives to implement the specified behaviour. This typically (as of 2004) requires the synthesizer to ignore the expression of any timing constructs in the text. The ability to have a synthesizable subset of the language does not itself make a hardware description language.

Designing a system in HDL is generally much harder and more time consuming than writing a program that would do the same thing using a programming language like C. Consequently, there has been much work done on automatic conversion of C code into HDL, but this has not reached a high level of commercial success as of 2004.

1 History of HDLs
2 Design using HDL
3 Simulating and debugging HDL code
4 HDL and programming languages
5 Languages
- 5.1 Digital circuit design
- 5.2 Analog circuit design
6 See also
7 External links

[edit] History of HDLs

The first hardware description language was ISP developed at the Carnegie Mellon University in circa 1977. ISP was, however, more like a software programming language used to describe relations between the inputs and the outputs of the design. Therefore, it could be used to simulate the design, but not to synthesize it. In 1983 Data-I/O introduced ABEL. It was targeted for describing programmable logical devices and was basically used to design final state machines.

The first modern HDL, Verilog, was introduced by Gateway Design Automation in 1985. Cadence Design later acquired the rights to Verilog-XL, the HDL-simulator which would become the de-facto standard (of Verilog simulators) for the next decade. In 1987, a request from the U.S. Department of Defence led to the development of VHDL (Very High Speed Integrated Circuit Hardware Description Language.) Initially, Verilog and VHDL were used to document and simulate circuit-designs already captured in another form (such as a schematic file.) Logic synthesis, i.e. the software process of 'compiling' HDL-source files into a manufacturable gate/transistor-level netlist description, only began to replace digital schematic-capture when the design-sizes and software progressed to the point where they offered a clear productivity advantage.

Within a few years, both VHDL and Verilog became the dominant HDLs in the electronics industry. Among governmental and research institutions, VHDL enjoys greater adoption due to its origin. Older and less-capable proprietary HDLs fell out of use. But in the years since VHDL/Verilog's takeover, researchers worked on ways to improve VHDL and Verilog. For example, neither VHDL nor Verilog were suitable for analog-circuit or mixed-signal simulation. And neither was particularly well suited to describing recursively-generated logical structures. This has given birth to a few narrowly-scoped HDLs, which serve to augment (not replace) the incumbents VHDL/Verilog. And equally important, it has also led to the continuing refinement and revision of the VHDL and Verilog language specification.

[edit] Design using HDL

HDLs are used to design two kinds of systems. First, they are used to design a dedicated integrated circuit, such as a processor or other kind of digital logic chip. In this case, HDL specifies a model for the expected behaviour of a circuit before that circuit is designed and built. The end result is a silicon chip that would be manufactured in a fab.

The second use involves programming the programmable logic devices, such as the FPGAs. The HDL code is fed into a logic compiler, and the output is uploaded into the device. The unique property of this process, and of the programmable logic in general, is that it is possible to alter the code many times, compile it, and upload into the same device for testing.

[edit] Simulating and debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. An HDL program may be tested in hardware, such as by uploading it into a programmable logic device or even by producing a chip based on its specification. However, this is generally a very time-consuming and costly process, and generally the bulk of testing and debugging is done using a program called simulator. The simulator maintains a resettable "clock", similar to the real clock of a digital device, and allows the designer to print out the values of various registers over time in order to debug the code.

[edit] HDL and programming languages

An HDL is analogous to a software programming language, but with subtle differences. Both types of language are processed by a compiler (usually called a synthesizer in the HDL case). An HDL compiler often works in several stages, first producing a logic description file in a proprietary format, then converting that to a logic description file in the industry-standard EDIF format, then converting that to a JEDEC-format file. The JEDEC file contains instructions to a PLD programmer for building logic.

On the other hand, a software compiler generates instructions to a microprocessor for moving data. The difference between HDLs and software languages is becoming less distinct as reconfigurable systems are beginning (in 2002) to combine features of both.

The current trend is to move away from proprietary HDLs and towards the two leading standards, VHDL and Verilog HDL.

[edit] Languages

[edit] Digital circuit design

The two most widely-used and well-supported HDL varieties used in industry are VHDL and Verilog. Others include:

ABEL ("Advanced Boolean Expression Language")
AHDL (Altera HDL, a proprietary language from Altera)
Confluence (a functional programming language for reactive system design).
CUPL (a proprietary language from Logical Devices, Inc.)
HDCaml (a hardware description language based on the Objective Caml programming language)
Hardware Join Java based on Join Java
HML (based on SML)
Hydra (a hardware description language based on Haskell and developed at the University of Glasgow)
JHDL (based on Java)
Lava (based on Haskell)
Lola (a simple language used for teaching)
MyHDL (based on Python)
PALASM (for Programmable Array Logic (PAL) devices)
Ruby (hardware description language)
RHDL (based on the Ruby programming language)
CoWareC, a C-based HDL by CoWare. Now discontinued in favor of SystemC
SystemVerilog, a superset of Verilog, with enhancements to address system-level design and verification
SystemC, a standardized class of C++ libraries for high-level behavioral and transaction modeling of digital hardware at a high level of abstraction, i.e. system-level