Instruction set matrix
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In computer architecture, an instruction set matrix is a group of elements organized in columns and rows, which refer to multiple instruction formats.
Some computer architectures support multiple instruction formats. For example, certain versions of the ARM and MIPS microprocessors support both a 32-bit instruction set as well as a different 16-bit instruction set.[1] Current compilers and debuggers for these architectures use various heuristics to determine how to interpret the ISA to which a particular instruction belongs. These heuristics are arranged in a set of columns and rows in computer logic, similar to this:
| 16-bit | 32-bit |
|---|---|
| instruction set A | instruction set 1 |
| instruction set B | instruction set 2 |
Thus, for a 32-bit computer to run and compile a set of instructions from set A in 16-bit format, it would run instruction set 1.
For architectures which support only a single architecture, such as the computers in cars and cell phones, no such instruction set is needed.
[edit] References
- ^ Application Specific Array Processors, 1991. Proceedings of the International Conference on, ISBN 0-8186-9237-5
