Render Output unit
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The Render Output Unit, often abbreviated as "ROP", and sometimes called (perhaps more properly) Raster Operations Pipeline, is one of the final steps in the rendering process of modern 3D accelerator boards. The pixel pipelines take pixel and texel information and process it, via specific matrix and vector operations, into a final pixel or depth value. The ROPs perform the transactions between the relevant buffers in the local memory - this includes writing or reading values, as well as blending them together.
Historically the number of ROPs, texture units, and pixel shaders have been equal. The ATI Radeon 9700, for example, was well served by its 8 texture units (TMU), 8 pixel shaders, and 8 ROPs. However, as of 2004, several cards have decoupled these areas to allow optimum transistor allocation for application workload and available memory performance. The nVidia GeForce 6600 uses 8 TMUs and 8 pixel shaders, but with only 4 ROPs, resulting in a chip performing as well as an 8×8×8 combination. The 6600 has less memory bandwidth than a Radeon 9700, but because of the improvements in its efficiency, and a higher clock speed, it outperforms the older card. The "NV42" variant of GeForce 6, used for GeForce 6800 GS and GeForce 6800 Go, does the same with a 12×12×8 configuration. The new GeForce 7600 again uses a 12×12×8 combination.
In the future it is expected that graphics processors will continue to decouple the various parts of their architectures to enhance their adaptability to future graphics applications. This design also allows chip makers to build a modular line-up, where the top-end card is essentially using the same logic as the low-end product.
