Silicon on insulator
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Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices [2]. The precise thickness of the insulating layer and topmost silicon layer also vary widely with application.
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[edit] Industry need
The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microlectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:
- Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
- Resistance to latchup due to complete isolation of the n- and p- well structures.
From a manufacturing perspective, SOI substrates are compatible with most conventional fab processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 - 15% increase to total manufacturing costs.[3]
[edit] Manufacture of SOI wafers
SiO2-based SOI wafers can be produced by several methods:
- SIMOX - Separation by IMplantation of OXygen - uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.[citation needed]
- Wafer Bonding[citation needed] - the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer. One prominent example of a wafer bonding process is the Smart Cut™ method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
- Seed methods[citation needed] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.
An exhaustive review of these various manufacturing processes may be found in reference [1]
[edit] Use in the microelectronics industry
Examples of microprocessors built on SOI technology include AMD's 130 nm and 90 nm Opteron microprocessors, as well as the 90 nm IBM-based processors used in the Xbox 360, PlayStation 3 and Wii. Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors, are built using conventional bulk CMOS technology.
[edit] References
- ^ a b Celler, G.K., Cristoloveanu, S. J App Phys, 93, 4955 (2003)
- ^ SOI design: analog, memory and digital techniques by Andrew Marshall & Sreedhar Natarajan, Kluwer Academic, 2002, ISBN 0-7923-7640-4
- ^ http://news.com.com/IBM+touts+chipmaking+technology/2100-1001_3-254983.html
[edit] External links
- AMDboard - a site with extensive information regarding SOI technology
- Soitec - The official website of Soitec
- Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec.
