XOR gate
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| INPUT A B |
OUTPUT A XOR B |
|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The XOR gate is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table to the right. A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results.
This function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate.
[edit] Symbols
There are two symbols for XOR gates: the 'military' symbol and the 'rectangular' symbol. For more information see Logic Gate Symbols
Hardware description and pinout ==
XOR gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4070, which includes four independent, two-input, XOR gates. The 4070 replaces the less reliable 4030, but keeps the pinout. The pinout diagram is as follows:
1 Input A1 2 Input B1 3 Output Q1 4 Input A2 5 Input B2 6 Output Q2 7 VG 8 Input A3 9 Input B3 10 Output Q3 11 Input AA 12 Input B4 13 Output Q4 14 VCC |
This device is available from most semiconductor manufacturers such as Philips. It is usually available in both through-hole DIL and SOIC format. Datasheets are readily available in most Datasheet Databases.
[edit] Alternatives
If no specific XOR gates are available, one can be made from four NAND or five NOR gates in the configurations shown below. Interestingly, any logic gate can be made from a combination of NAND gates or a combination of NOR gates.
[edit] More than two inputs
The case of a three, or more, input XOR operation tends to be an ill-considered case. An XOR operation with three simultaneous inputs is not so easily expressed in most popular programming languages. When expressed as successive binary operations the result is a simple parity, giving a TRUE result for any odd number of TRUE inputs.
When taken as a multi-input black box whose operation follows the formal definition and yields the result TRUE when one, and only one, of its inputs is TRUE, the behaviour is inconsistent with the successive binary mode. For example; in the case where three inputs are all TRUE (as shown on the right, in the IEC symbology to emphasise the definition) the result would have to be FALSE because it does not meet the condition that "only one of its inputs is TRUE".
