SuperH
From Wikipedia, the free encyclopedia
The SuperH (or SH) is brandname of a certain microcontroller and microprocessor architecture. The SuperH is fundamentally a 32-bit load/store RISC architecture found in a large number of embedded systems.
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[edit] History
The SuperH processor core family was first developed by Hitachi in the early 90's. Many microcontrollers and microprocessors were based on this architecture.
Hitachi was developing a complete set of instruction set upward compatible CPU cores. Originally, the SH-1 and the SH-2 were used in the Sega Saturn and Sega 32X and then later in many other microcontrollers used in many other embedded applications. These cores use a 16-bit instruction set, though register length and data paths are 32-bit, which gave it an excellent code density. At the time, memory was very expensive.
A few years later, the SH-3 core was added to this family of CPU cores extending the original cores mainly by another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP core. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core, then called SH-DSP.
For the Sega Dreamcast, Hitachi was then developing the SH-4 architecture. This was a massive extension of the previous cores. Superscalar (2-way) instruction execution and a parallel vector floating point unit were the highlights of this architecture. This CPU core was then also used in many chipsets for embedded applications requiring a very high performance. SH-4 based standard chips were roughly introduced around 1998.
A bit later, Hitachi and ST Microelectronics formed the IP company SuperH, Inc which was going to license the SH-4 core to other companies and was developing the SH-5 architecture. The first move of SuperH into the 64-bit area. SuperH, Inc. sold the IP of these CPU cores.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; recent ARM processors have a 16-bit Thumb mode, and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
After that, the evolution of the SuperH architecture still continued. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.
Today, the SuperH CPU cores, architecture and products are with Renesas Technology, a merger of the Hitachi and Mitsubishi semiconductor groups. See further details under Renesas.
[edit] Models
The family of SuperH CPU cores include:
- SH-1 - used in microcontrollers for deeply embedded applications (CD-ROM drives, major appliances, etc)
- SH-2 - used in microcontrollers with higher performance requirements, also used in automotive such as engine control units or in networking applications
- SH-DSP - initially developed for the mobile phone market, used later in many consumer applications requiring DSP performance for JPEG compression etc
- SH-3 - used for mobile and handheld applications, strong in Windows CE applications and market for many years in the car navigation market
- SH-3-DSP - used mainly in multimedia terminals and networking applications, also in printers and fax machines
- SH-4 - used whenever high performance is required such as car multimedia terminals, video game consoles, or set-top boxes
- SH-5 - used in high-end multimedia applications
- SH-X - mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
- SH-Mobile - SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI, this is a solution to ease system development and realise significant performance improvement.
The SuperH cores are supported worldwide by many RTOS and tool vendors.
[edit] Distinctions
- Scalability
- Cost efficient
- Optimised for embedded applications
- High performance
[edit] See Also
[edit] Debuggers
[edit] RTOS
[edit] External links
Linux for SuperH
- http://www.kpitgnutools.com, Official free SH GNU Toolchain with Support
- http://www.linux-sh.org/, http://linuxsh.sourceforge.net/
- http://www.sh-linux.org/ gcc toolchain
- http://www.shlinux.com/ MPC Data SHLinux support
Linux distributions for SuperH
- Jlime (Jornada Linux Mobility Edition) has working distribution for HP Jornada 620LX/660LX/680/690 handhelds; JLime is probably the largest SuperH distribution.
- Gentoo Linux
- STLinux
- T2 SDE T2 System Development Environment
NetBSD on SuperH
OpenBSD on SuperH
| RISC |
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| Power Architecture · ARM architecture · DEC Alpha · Atmel AVR · MIPS architecture · PA-RISC · Parallax Propeller · PIC microcontroller · SPARC · SuperH · XAP processor · I960 · Motorola 88000 |
