Blackfin

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Blackfin refers to a family of 16/32-bit microprocessors and incorporate Digital Signal Processor (DSP) capabilities and features more commonly found in micro-controllers in a power-efficient architecture. The result is a low-power, unified processor architecture that can run operating systems while simultaneously handling complex numeric processing tasks like real time H.264 video encoding, for example.

The processors come on several varieties of hardware development kits and a community supported Linux port is available. Currently the microprocessor is manufactured by Analog Devices Inc (ADI).

Contents 1 Architecture Details 2 Architecture Features 2.1 Core Features 2.2 Memory and DMA 2.3 Micro-controller Features 2.4 Media Processing Features 3 Peripherals 4 Development Tools Software 5 Supported Operating Systems, RTOSs & Kernels 6 See also 7 External links

[edit] Architecture Details

Blackfin processors use a 32-bit RISC MCU programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The Blackfin processor architecture was announced in December, 2000 and first demonstrated at the Embedded Systems Conference in June, 2001.

The Blackfin architectures takes the best of ADI's older SHARC architecture, and the best of Intel's Xscale architecture and puts them into a single core, combining Digital Signal Processing (DSP) and micro-controller functionality. There are many differences in the core architecture between Blackfin/MSA and Xscale/ARM or SHARC, but the combination provides improvements in performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses a number of different models of CPU, each with advantages for particular applications. The Blackfin family is summarized in the following table.

Processor	Max. Clock	Cores	Instr L1 SRAM/Cache	Data L1 SRAM/Cache	L2 SRAM	On-chip Flash	Host Port	Code Security	Ethernet MAC	SD/SDIO	16-bit PPIs	18/24-bit PPIs	SDRAM	USB	ATAPI	CAN	I²C (TWI)	SPI	UART	SPORT	GPIO	MXVR
ADSP-BF542	600 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	Yes	-	1	1	0	DDRx16	1	1	1	1	2	3	3	152 pins	-
ADSP-BF544	533 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	64KB	-	Yes	Yes	-	-	1	1	DDRx16	-	-	2	2	2	3	3	152 pins	-
ADSP-BF548	600 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	128KB	-	Yes	Yes	-	1	1	1	DDRx16	2.0/OTG	1	2	2	3	4	4	152 pins	-
ADSP-BF549	533 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	128KB	-	Yes	Yes	-	1	1	1	DDRx16	2.0/OTG	1	2	2	3	4	4	152 pins	1
ADSP-BF531	400 MHz	1	32KB Instr (16KB cache)	16 KB Data (16KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	-	-	1	1	2	16	-
ADSP-BF532	400 MHz	1	48KB Instr (16KB cache)	32 KB Data (32KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	-	-	1	1	2	16	-
ADSP-BF533	600 MHz	1	80KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	-	-	1	1	2	16	-
ADSP-BF534	500 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	1	1	1	1	2	48	-
ADSP-BF536	500 MHz	1	64KB Instr (16KB cache)	32 KB Data (32KB cache) 4KB scratch	-	-	-	-	1	-	1	-	SDRx16	-	-	1	1	1	1	2	48	-
ADSP-BF537	600 MHz	1	64KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	-	1	-	1	-	SDRx16	-	-	1	1	1	1	2	48	-
ADSP-BF538	500 MHz	1	80KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	1	2	3	3	4	54	-
ADSP-BF538F	500 MHz	1	80KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	512KB 1024KB	-	-	-	-	1	-	SDRx16	-	-	1	2	3	3	4	54	-
ADSP-BF539	500 MHz	1	80KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	-	-	-	-	-	1	-	SDRx16	-	-	1	2	3	3	4	38	1
ADSP-BF539F	500 MHz	1	80KB Instr (16KB cache)	64 KB Data (32KB cache) 4KB scratch	-	512KB 1024KB	-	-	-	-	1	-	SDRx16	-	-	1	2	3	3	4	38	1
ADSP-BF561	600 MHz	2	64KB Instr (16KB cache) per core	64 KB Data (32KB cache) 4KB scratch per core	128KB	-	-	-	-	-	2	-	SDRx32	-	-	-	-	1	1	2	48	-
ADSP-BF535	350 MHz	1	16KB Instr	32KB Data 4KB scratch	256KB	-	-	-	-	-	-	-	SDRx16	1.1	-	-	-	2	2	2	16	-

In addition to the features in the table above, all Blackfin processors have the following peripherals

• Debug/JTAG Interface for in-system debugging
• Real-time clock
• Internal core voltage switching regulator
• Watchdog timer
• Timers/PWM outputs/PWM capture ports
• Core timer (runs at core clock speed)

[edit] Architecture Features

[edit] Core Features

The heart of the Blackfin depends on the person looking at it.

• For some, it is a DSP. It combines two 16-bit hardware MACs, two 40-bit ALUs, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization of the compiler (or of the programmer).
• For others, it is yet another RISC core. It includes memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA also features a high level of expressiveness, allowing the assembly programmer (or compiler) to highly optimize an algorithm to the hardware features present.

[edit] Memory and DMA

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers all reside in this 32-bit address space.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard Architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses which allows for high sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache (independently).

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR FLASH, NAND FLASH and SRAM. Some Blackfin also include mass-storage interfaces such as ATAPI, and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the significant core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which enables very high throughput for applications that can take advantage of it such as real-time standard-definition (D1) video encoding and decoding.

[edit] Micro-controller Features

The Blackfin architecture contains a number of attributes commonly found on microprocessors and micro-controllers. These features allow Blackfin to efficiently and securely run many commercial and open-source operating systems.

• Memory Management Unit : All Blackfin processors contain an MMU which provides protection and caching strategies across the entire memory space. The MMU allows Blackfin to support many full-features operating systems, RTOSs and kernels. The Blackfin MMU does not provide address translation thus it does not support virtual memory. This is why Blackfin currently does not support operating systems requiring virtual memory such as WinCE, QNX, or full Linux.

• User/Supervisor Modes : Blackfin supports three run-time modes : supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MMU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc) an exception will be thrown and the kernel will then be able to shut down the offending thread/process.

• Variable-Length, RISC-Like Instruction Set : Blackfin supports 16, 32 and 64-bit instructions. Commonly-used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32 and 64-bit opcodes. This variable length opcode encoding allows Blackfin to achieve good code density equivalent to modern micro-processor architectures.

[edit] Media Processing Features

The Blackfin instruction set contains media processing extensions to help accelerate pixel processing operations commonly used in video and image compression/decompression algorithms.

[edit] Peripherals

Blackfin processors contain a wide array of connectivity peripherals.

• USB 2.0 OTG (On-The-Go)
• ATAPI
• MXVR : a MOST (Media Oriented Systems Transport) Network Interface Controller. MOST is a registered trademark of SMSC.
• PPI (Parallel Peripheral Interface) : A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 65MHz and can be configured from 8 to 16-bits wide.
• SPORT : A synchronous, high speed serial port that can support TDM, I2S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
• CAN : A wide-area, low-speed serial bus that is fairly popular in automotive and industrial electronics.
• UART (Universal Asynchronous Receiver Transmitter) : allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc), MIDI devices, IRDA devices.
• SPI : A staple of (relatively) high-speed embedded electronics.
• I²C (also known as TWI (two-wire interface)) : A lower speed, shared serial bus.

Because all of the peripheral control registers are memory-mapped in the normal address space, they are quite easy to set-up.

[edit] Development Tools Software

ADI provides its own software development toolchain, CROSSCORE (VisualDSP++), but other options are also available, such as Green Hills Software's MULTI IDE, the GNU GCC Toolchain for the Blackfin processor family, or National Instruments' LabVIEW Embedded Module.

[edit] Supported Operating Systems, RTOSs & Kernels

Blackfin supports numerous commercial and open-source operating systems.

OS/RTOS/Kernels on Blackfin

Title	Type	Home Page	Comments
µcLinux	Open-Source/GPL	http://blackfin.uclinux.org wiki : http://docs.blackfin.uclinux.org
ThreadX	Commercial	http://www.rtos.com
Nucleus	Commercial	http://www.mentor.com
Fusion	Commercial	http://www.unicoi.com/fusion_rtos/rtos_blackfin.htm
µC/OS-II	Open-Source	http://www.micrium.com/
velOSity Microkernel	Commercial	http://www.ghs.com
INTEGRITY	Commercial	http://www.ghs.com
RTEMS	Open-Source/GPL	http://www.rtems.com/
T2 SDE	Open-Source/GPL	http://www.t2-project.org/architectures/blackfin.html
VDK	Commerical	http://www.analog.com/blackfin	ADI's real-time kernel. Ships with VisualDSP++.

[edit] See also

• SHARC
• TigerSHARC

[edit] External links

• Blackfin processor website
• Blackfin Forum, a web community for users of the processors
• uClinux for Blackfin, various open source projects for Blackfin
• Express Logic RTOS manufacturer for various processors, including Blackfin.
• Cambridge Signal Processing Computer modules based on the Blackfin.
• UoC ECE-ADI-Project University of Calgary project homepages (links to other university projects and helpful material).