FlexRay

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FlexRay is a new automotive network communications protocol under development by the FlexRay Consortium. It is positioned above CAN and MOST both in terms of performance and price.

Its prominent features are:

• high data rates (10 megabits per second)
• time triggered behavior
• redundancy, safety, and fault-tolerance

The protocol specifications are in review stage. The first production vehicle with FlexRay will be the 2006 BMW X5, though it will only be used for the pneumatic damping system. Full use of FlexRay is expected in 2008.

The FlexRay Consortium is made up of the following major members:

• Volkswagen
• BMW
• DaimlerChrysler
• General Motors
• Robert Bosch GmbH
• NXP Semiconductors
• Freescale, formerly part of Motorola

Contents 1 Details 1.1 Clock 1.2 Bits on the bus 1.3 Sampled bits 1.4 Frame 1.5 Clock synchronization

[edit] Details

[edit] Clock

FlexRay system consists of a bus and processors (ECU, electronic control units). Each ECU has an independent clock. The clock drift must be no more than 0.15% from the reference clock, so the difference between the slowest and the fastest clock in the system is no larger than 0.3%.

This means if ECU-s is a sender and ECU-r is a receiver, then for every 300 cycles of the sender there will be between 299 and 301 cycles of the receiver. The clocks are resynchronized frequently enough to assure that this doesn't cause any problems.

[edit] Bits on the bus

At each time, only one ECU writes to the bus. Each bit to be sent is held on the bus for 8 cycles. The receiver keeps a buffer of the last 5 samples, and uses the majority of the last 5 samples as the input signal. If there weren't any errors on the bus this means the signal will simply be delayed 2 cycles.

Single-cycle transmission errors may affect results near boundary of the bits, but will not affect cycles in the middle of the 8-cycle region.

[edit] Sampled bits

The value of the bit is sampled in the middle of the 8-bit region . The errors are moved to the extreme cycles, and the clock is synchronized frequently enough for the drift to be small. (drift is smaller than 1 cycle per 300 cycles, and during transmission the clock is synchronized more often than once every 300 cycles).

[edit] Frame

All the communication is sent in form of frames. The message consists of bytes , packed in the following way:

• Transmission Start Signal (TSS) - bit 0
• Frame Start Signal (FSS) - bit 1
• m times:
  • Byte Start Signal 0 (BSS0) - bit 1
  • Byte Start Signal 1 (BSS1) - bit 0
  • 0-th bit of i-th byte
  • 1-th bit of i-th byte
  • 2-th bit of i-th byte
  • ...
  • 7-th bit of i-th byte
• Frame End Signal (FES) - bit 0
• Transmission End Signal (TES) - bit 1

If nothing is being communicated, the bus is held in state 1 (high voltage), so every receiver knows that the communication started when the voltage drops to 0.

The receiver knows when the message is complete by checking whether BSS0 (1) or FES (0) was received.

Note that 8-cycle per bit has nothing to do with bytes. Each byte takes 80 cycles to transfer. 16 for BSS0 and BSS1 and 64 for its bits. Also note that BSS0 has value 1, and BSS1 has value 0.

[edit] Clock synchronization

Clocks are resynchronized when the voted signal changes from 1 to 0, if the receiver was in either idle state or expecting BSS1.

So the clock is synchronized when the transmission starts and between BSS0 and BSS1. As we're synchronizing on the voted signal, small transmission errors during synchronization that affect the boundary bits may skew the synchronization no more than 1 cycle. As there are at most 88 cycles between synchronization (BSS1, 8 bits of the last byte, FES and TES - 11 bits of 8 cycles each), and the clock drift is no larger than 1 per 300 cycles, the drift may skew the clock no more than 1 cycle. Small transmission errors during the receiving may affect only the boundary bits. So in the worst case the two middle bits are correct, and thus the sampled value is correct.

Here's an example of a particularly bad case - error during synchronization, a lost cycle due to clock drift and error in transmission.

Errors that happened in the example

• Because of a single-bit error during synchronization, the synchronization was delayed by 1 cycle
• Receiver clock was slower than sender clock, so receiver missed one cycle (marked X). This won't happen again before the next synchronization due to limits on maximum allowable clock drift.
• Because of a single-bit error during transmission, a bit was voted wrongly near the result.

In spite of so many errors, the communication was received correctly.

The lime cells are sampling points. All except for the first are synchronized by the 1->0 edge in the shown transmission fragment.

Signal to be sent	1								0								1								0								1
Signal sent	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	1	1
On the bus	1	1	1	1	1	1	1	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0	0	0	0	0	0	1	0	1	1
Received	1	1	1	1	1	1	1	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	X	1	0	0	0	0	0	0	1	0	1	1
5-maj voted			1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	1	1	1	1	X	1	1	1	0	0	0	0	0	0	0	1