加法器
维基百科，自由的百科全书
在電子學中，加法器是一種數位電路，其可進行數字的加法計算。在現代的電腦中，加法器存在於算術邏輯單元（ALU）之中。 加法器可以用來表示各種數值，如︰BCD、加三碼，主要的加法器是以二進制作運算。由於負數可用二的補數來表示，所以加減器也就不那麼必要。
目录 |
[编辑] 加法器的類型
以單位元的加法器來說，有兩種基本的類型︰半加器和全加器。
半加器有兩個輸入和兩個輸出，輸入可以標識為 A、B 或 X、Y，輸出通常標識為合 S 和進位 C。A 和 B 經 XOR 運算後即為 S，經 AND 運算後即為 C。
全加器引入了進位值的輸入，以計算較大的數。為區分全加器的兩個進位線，在輸入端的記作 Ci 或 Cin，在輸出端的則記作 Co 或 Cout。
半加器簡寫為 H.A.，全加器簡寫為 F.A.。
[编辑] 半加器
半加器有兩個二進制的輸入，其將輸入的值相加，並輸出結果到合（Sun）和進位（Carry）。半加器雖能產生進位值，但半加器本身並不能處理進位值。
下表為半加器的真值表︰
| 輸入 | 輸出 | ||
|---|---|---|---|
| A | B | C | S |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
[编辑] 全加器
A + B + 進位(輸入) = 合 + 進位(輸出)
全加器三個二進制的輸入，其中一個是進位值的輸入，所以全加器可以處理進位值。全加器可以用兩個半加器組合而成。
| 輸入 | 輸出 | |||
|---|---|---|---|---|
| A | B | Ci | Co | S |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |
注意，進位輸出端的最末個 OR 閘，也可用 XOR 閘來代替，且無需更改其餘的部分。因為 OR 閘和 XOR 閘只有當輸入皆為 1 時才有差別，而這個可能性已不存在。
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and or the two carry outputs. Equivalently, S could be made the three-bit xor of A, B, and Ci and Co could be made the three-bit majority function of A, B, and Ci. The output of the full adder is the two-bit arithmetic sum of three one-bit numbers.
[编辑] 多位元加法器
[编辑] 漣波進位加法器
Ripple carry adder
When multiple full adders are used with the carry ins and carry outs chained together then this is called a ripple carry adder because the correct value of the carry bit ripples from one bit to the next.
It is possible to create a logical circuit using several full adders to add multiple-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.
The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Following the path from Cin to Cout shows 2 gates that must be passed through. Ergo, a 32-bit adder requires 31 carry computations and the final sum calculation for a total of 31 * 2 + 1 = 63 gate delays.
[编辑] 前視進位加法器
Carry look-ahead adders
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry lookahead adders. They work by creating Propagate and Generate signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry lookahead architectures are the Manchester carry chain and the Brent-Kung adder.
Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block.
Other adder designs include the conditional sum adder, carry skip adder, and carry complete adder.
[编辑] 前視進位單元
Lookahead Carry Unit
By combining multiple carry look-head adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses 16 4-bit CLAs with two levels of LCUs.
[编辑] 3:2 壓縮器
We can view a full adder as a 3:2 compressor: it sums three one-bit inputs, and returns the result as a single two-bit number. Thus, for example, an input of 101 results in an output of 1+0+1=10 (2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 compressor.
3:2 compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the Carry save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.
[编辑] 參閱
- Carry look-ahead adder
- Carry-save adder
- Carry bypass adder
- Carry select adder
- Ling adder
- Kogge-Stone Adder
- Brent-Kung adder
- Serial binary adder
- Adding machine
- Adder-subtracter
- Subtracter (electronics)
[编辑] 外部連結
- Hardware algorithms for arithmetic modules, includes description of several adder layouts with figures.
